The present invention relates to semiconductor integrated circuits, e.g., a technique advantageous for dynamic RAMs (random access memories) which are directed to higher speed and lower power consumption.
Japanese unexamined patent publication No. 8-181292 discloses an example of dynamic RAMs which a hierarchical word line configuration and a triple well structure including an N-well of a great depth.
In a dynamic RAM, a plurality of internal voltages are developed from a power supply voltage supplied through an external terminal and are supplied to internal circuit blocks. For example, a method of operating internal circuits using a voltage (3V) as a result of a voltage drop from an external power supply voltage VDD (5V) has been widely used since the advent of 16 Mbit dynamic RAMS in order to maintain the reliability of fine devices and to reduce power consumption. The 64 Mbit generation is directed to lower operating voltages in internal circuits, e.g., an external voltage VDD drops to 3.3 V to supply a low voltage on the order of 2.5 V to capacitors of memory cells, and, further, peripheral circuits are also operated at the dropped voltage.
A dynamic memory cell must be formed to have a high threshold voltage in order to prevent a reduction of information retention time attributable to a leakage current in an off state and a leak current caused by the lifting of a word line. It is desirable to reduce the operating voltage of internal circuits other than the memory cells to reduce power consumption, and the threshold voltage of MOSFETs (hereinafter, imply MISFETs according to general recognition) is preferably low in order to maintain a desired operating speed at such a low voltage.
In conventional dynamic RAMs, in order to satisfy the conflicting requirements described above, a MOSFET having a relatively high threshold voltage is formed in consideration to the information retention time at the memory cell and the operating speed of peripheral circuits as described above. The three-well structure described above electrically isolates P-type well regions where MOSFETs of memory cells are formed and P-type well regions or a substrate where MOSFETs of peripheral circuits are formed; a negative backward bias voltage is supplied to channel regions of MOSFETs that form address selection MOSFETs of memory cells to make a correction to increase a threshold voltage thereof; the ground potential of the circuit is supplied to channel regions of MOSFETs forming the peripheral circuits; and the impurity concentration of the channel regions is corrected to a lower value to make an adjustment to reduce the threshold voltage using an ion implantation technique.